Search - serial vhdl

[VHDL-FPGA-Verilog] 用VHDL语言在CPLD上实现串行通信

Description: 用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication
Platform: | Size: 4096 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

Description: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
Platform: | Size: 10240 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] chengxu(vhdl)

Description: 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
Platform: | Size: 548864 | Author: 黄鹏飞 | Hits:

[VHDL-FPGA-Verilog] uart-verilog-vhdl

Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Platform: | Size: 294912 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: xilinx Sparten3E 串行通信及lcd字符显示-xilinx Sparten3E characters serial communication and lcd display
Platform: | Size: 2048 | Author: ronghy | Hits:

[VHDL-FPGA-Verilog] uart_vhdl

Description: vhdl的异步串口代码，可以方便以致在不同的FPGA中-asynchronous serial VHDL code, can easily result in different FPGA in
Platform: | Size: 18432 | Author: 李冰 | Hits:

[VHDL-FPGA-Verilog] uart(serial)-200792511240998

Description: 基于vhdl 的串行接口具有完整的程序-VHDL-based serial interface with a complete process
Platform: | Size: 265216 | Author: weixing | Hits:

Description: 串口通讯协议，你您可以自己建个工程，再将需要的VHDL文本，添加到工程中，理解程序在仿真！-Serial communication protocol, you can build your project, and then need VHDL text, added to the project, understand the procedures in the simulation!
Platform: | Size: 10240 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] 080513154000

Description: 并行转串行的VHDL描述：基于FPGA的SPI发送模块的设计-Parallel to serial VHDL description: Based on the FPGA to send the SPI module
Platform: | Size: 95232 | Author: yaoqinghua | Hits:

[VHDL-FPGA-Verilog] serial

Description: 串行口数据传输实验，vhdl源代码，完成信号发生，串并转换，检测电路-Serial port data transmission experiment, vhdl source code, complete the signal occurred, SERDES, detection circuit
Platform: | Size: 1024 | Author: yew | Hits:

[VHDL-FPGA-Verilog] uart_serial

Description: UART接口的VHDL源代码，成功应用于SOC项目开发中，请勿用于商业用途。-UART interface of the VHDL source code, successfully applied in the development of SOC projects, not for commercial purposes.
Platform: | Size: 12288 | Author: xiaojian | Hits:

[VHDL-FPGA-Verilog] uart_v11

Description: uart串口的vhdl语言程序。本人调试过，非常好用-serial UART VHDL Language Program. I debug, and very easy to use
Platform: | Size: 43008 | Author: hjj | Hits:

[VHDL-FPGA-Verilog] RS232uart(VHDL)

Description: 256字节深度的RS232串口程序,共分4个模块,顶层文件\FIFO程序\串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!
Platform: | Size: 5120 | Author: 温海龙 | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[Windows Develop] parell_to_serial

Description: 该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。-The module main is completed and the string conversion functions. System_clk which is an input parallel clock frequency, it is the serial clock serial_clk eight times. byte_data_en is a parallel data input enable signal, byte_data is a parallel data input. serial_data is converted serial data, bit_data_enable is the serial data signal.
Platform: | Size: 1024 | Author: huangdecheng | Hits:

[VHDL-FPGA-Verilog] uart

Description: VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过-VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
Platform: | Size: 223232 | Author: 李特威 | Hits:

[VHDL-FPGA-Verilog] serial

Description: 基于VHDL的串口通信基于VHDL的串口通信-VHDL-based serial communication based on VHDL Serial Communication
Platform: | Size: 377856 | Author: 戴明 | Hits:

[Embeded-SCM Develop] serial

Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --制器，10个bit是1位起始位，8个数据位，1个结束 --位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 --划分为8个时隙以使通信同步. --程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome" --字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制 --数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at - PC machine on the installation of a serial debugging tools to verify the function of the procedure. - Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control - System, and 10 bit is a start bit, 8 data bits, 1 Ending - Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real - Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are - 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time - Is divided into eight time slots in order to enable synchronous communication. - Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome" - String (serial debug tools is set to accept by way of A
Platform: | Size: 65536 | Author: johnson | Hits:

[Other] serial

Description: 利用VHDL语言编写的串口程序，可以在Quartus2环境下编译下载-Use the serial language VHDL program can be compiled in an environment Quartus2 Download
Platform: | Size: 335872 | Author: 爱涛 | Hits:

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

Description: 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用-String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
Platform: | Size: 1024 | Author: 随风 | Hits:

« 12 3 4 5 6 7 8 9 10 ... 35 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] 用VHDL语言在CPLD上实现串行通信

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

[VHDL-FPGA-Verilog] chengxu(vhdl)

[VHDL-FPGA-Verilog] uart-verilog-vhdl

[VHDL-FPGA-Verilog] RS232

[VHDL-FPGA-Verilog] uart_vhdl

[VHDL-FPGA-Verilog] uart(serial)-200792511240998

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] 080513154000

[VHDL-FPGA-Verilog] serial

[VHDL-FPGA-Verilog] uart_serial

[VHDL-FPGA-Verilog] uart_v11

[VHDL-FPGA-Verilog] RS232uart(VHDL)

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

[Windows Develop] parell_to_serial

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] serial

[Embeded-SCM Develop] serial

[Other] serial

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

CodeBus www.codebus.net